Deshanand P. Singh

2006

EE

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8

EE

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA PLB Evaluation using Quantified Boolean Satisfiability: a study of optimality: IEE Proceedings on Computers and Digital Techniques: 427-432

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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA PLB Architecture Evaluation and Area Optimization Techniques using Boolean Satisfiability: IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems

EE

Deshanand P. Singh, Stephen Dean Brown: An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. Integration, the VLSI Journal.

2005

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Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Two-Stage Physical Synthesis for FPGAs.. CICC 2005: 171-178

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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA technology mapping: a study of optimality. DAC 2005: 427-432

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Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Incremental retiming for FPGA physical synthesis. DAC 2005: 433-438

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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL 2005: 19-24

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Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown: Post-Placement BDD-Based Decomposition for FPGAs. FPL 2005: 31-38

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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT 2005: 444-450

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Andrew C. Ling, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: FPGA Architecture Evaluation and Technology Mapping using Boolean Satisfiability. IWLS 2005: 399-406

2004

EE

Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown: Post-Placement Functional Decomposition for FPGAs. IWLS 2004: 114-118

2003

EE

Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown: Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI 2003: 28-33

EE

Deshanand P. Singh, Stephen Dean Brown: An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI 2003: 41-50

2002

EE

Deshanand P. Singh, Stephen Dean Brown: Constrained clock shifting for field programmable gate arrays. FPGA 2002: 121-126

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Deshanand P. Singh, Stephen Dean Brown: Integrated retiming and placement for field programmable gate arrays. FPGA 2002: 67-76

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Deshanand P. Singh, Stephen Dean Brown: Incremental placement for layout driven optimizations on FPGAs. ICCAD 2002: 752-759

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Deshanand P. Singh: Techniques for Timing Closure on High-Speed Field Programmable Gate Arrays. PhD: University of Toronto.

2001

EE

Deshanand P. Singh, Stephen Dean Brown: The case for registered routing switches in field programmable gate arrays. FPGA 2001: 161-169

Issued Patents

Deshanand P. Singh, Stephen Dean Brown, Terry P. Borer, Chris Sanford, Gabriel Quan: Method and apparatus for placement of components onto programmable logic devices: United States Patent 6,779,169.